1. Field of Invention
The field of the present invention relates in general to analog-to-digital (A/D) conversion. More particularly the present invention relates to a multi-stage pipelined A/D converter.
2. Description of the Related Art
Analog-to-digital (A/D) converters are used in a wide variety of applications including telecommunications, radar, medical imaging, seismology, etc. There are numerous architectures for implementing A/D conversion including: flash, multi-step, pipeline, interplating, and time-interleaved successive approximation. The pipelined technique offers minimal circuit complexity, silicon area and power consumption with relatively high throughput.
In a pipelined architecture, the first stage operates on the most recent sample inputted while subsequent stages operate on residues from the prior samples output from prior stages of the cascaded pipeline architecture.
FIG. 1A is a block diagram of a prior art pipelined A/D converter with three stages 110, 120, 130. The converter includes a sample and hold unit 106; first, second, and third stages respectively 110, 120, 130; and a common clock 108. Each stage makes a digital approximation of the amplitude of the analog sample presented to it and passes the amplified residue to the next stage where the process is repeated for the next most significant bits. In operation, an analog signal (e.g., channel 1) on line 102 is delivered to a first sample and hold element 106. The first stage makes the digital approximation of the most significant bits of the sampled signal and delivers that on bit line 112. The amplified residue is presented on signal line 114 to the intermediate stage 120. The intermediate stage generates a digital approximation of the most significant bits of the residue signal, which in this case corresponds to the intermediate significant bits of the sample obtained from channel 1. These intermediate significant bits are output on bit line 122 and the amplified residue is output on signal line 124. Signal line 124 provides the input to the final stage 130 which generates a digital signal corresponding to the most significant bits of the residue. These bits correspond with the least significant bits of the original sample of channel 1. These are output on bit line 132. The composite signal in serial or parallel form with a precision determined by the combined signals on bit lines 112, 122, and 132 is presented on digital signal line 104. The common clock 108 drives each of the above-discussed components in a synchronous relationship. Each operates at the same clock speed.
As shown in FIG. 1B, each stage contains a sample and hold (SH) 158, an A/D converter (ADC) 150, a digital-to-analog converter (DAC) 156, and a differencer 154. The functions implemented by the DAC, SH and differencer may be implemented by a multiplying digital-to-analog converter (MDAC) 152. Both the ADC 150 and the differencer 154 are coupled directly to the analog signal line 114. The ADC 150 generates a signal corresponding the most significant bits of the signal received on signal line 114. This signal is provided as an output on bit line 122 as well as an input to the DAC 156. The DAC converts these most significant bits to analog form and provides them to the negative input of differencer 154. The differencer outputs a residue signal corresponding to the difference between the input signal on line 114 and the most significant bits generated by ADC 150 on bit line 122. The output of the summer is identified as a residue which is passed to the SH device 158 for output on signal line 124. The SH device includes a gain element to amplify the residue.
The main advantage of pipelined ADCs are that they can provide high throughput rates and occupy small die areas. Both advantages stem from the concurrent operation of the stages; that is, at any time the first stage operates on the most recent sample, while all other stages operate on residues from previous samples. (The associated latency is not a limitation in many applications.) If the A/D are done with flash converters, pipelined architectures require only two main clock phases per conversion; therefore the maximum throughput rate can be high. Also, since the stages operate concurrently, the number of stages used to obtain a given resolution is not constrained by the required throughput rate. For multichannel applications, prior art pipelined A/D converters require proportionately larger die areas and have concurrently larger power dissipations.
What is needed is a A/D converter architecture with reduced die area and power dissipation for multichannel applications.